In the field of memories generally and E.sup.2 PROMs in particular there is increasing interest in the development of multi-level technologies, particularly at 2 bits/cell level. For these technologies, one of the most critical features is the control of the threshold voltage (Vt) distribution width. However, to date this control is not simple and is influenced by a number of variables both in the process and design, including tunnel oxide thickness, charge pump output voltage and junction avalanche voltages to name but a few. A limited number of schemes have been published which attempt to control these variables to acceptable levels (see, for example, "A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications" by Tae-Sung Jung et al., Samsung Electronics and "A 2.5V 256-Level Non-Volatile Analog Storage Device Using EEPROM Technology" by Hieu Van Tran et al., Information Storage Devices, both presented at ISSCC 1996). However, none of these published schemes are truly self-limiting and are still very dependent on a stable and well characterised process/design to yield tight and repeatable Vt distributions.
One proposed self-limiting scheme for Fowler-Nordheim (FN) programmed E.sup.2 PROMs has been published in GB patent publication GB-A-2,304,947. This scheme relies on the fact that as an E.sup.2 PROM cell is programmed, the cell Vgs voltage increases. If the programming biasing is set appropriately, the cell will conduct at a given level of programming and allow current to flow down the bitline to a biased array ground node, as shown in FIG. 2. Due to resistive drops down the bitline programming path (and finite charge pump output impedance), the programming voltage at the floating gate transistor drain will drop as the cell begins to conduct, and hence will limit the final programmed Vt. If different array ground biases are utilised, then this scheme can be used to generate multi-level states and together with a multi-level sensing scheme, form the core of a multi-level E.sup.2 PROM module.
However, the scheme described in GB-A-2,304,947 has a number of limiting factors which have so far prevented it from being developed into a practical dense EEPROM array. These are as follows:
The scheme provides no obvious means of programming multiple bits/bytes (to different states) in parallel whilst using a common array ground and single high voltage charge pump. PA1 The absolute drop in bitline voltage during programming depends not only on the target programmed cell turning on, but also on the leakage from unselected cells in the common bitline and common rowline and the number of cells under programming bias that are shared by the same bitline driver. PA1 In practice, the drop in bitline voltage slows the rate of programming and will not stop programming completely. Therefore, additional control is required to disable drive to bitlines where the cell has reached its target, in order that tight Vt distributions are obtained.
Accordingly, a need exists for an electrically programmable memory and a method of programming an electrically programmable memory wherein the above mentioned disadvantages may be overcome or at least alleviated.